Memory circuits, that are based on magnetoresistive behavior of magnetic storage elements that are integrated typically with a complementary metal-oxide semiconductor (CMOS) technology, generally provide nonvolatility and an unlimited read and write endurance. A typical example is the magnetic random access memory (MRAM) circuit. The bit architecture in such circuits is generally based on a minimum size active transistor which serves as an isolation device in conjunction with a magnetic tunnel junction (MTJ) element or stack so as to define a bit for the memory circuit.
Though the aforesaid memory circuits have several desirable characteristics such as high speed, high density (i.e., small bit cell size), low power consumption, and no degradation over time, these have scalability issues. As the bit cells become smaller, the magnetic fields used for switching the memory state increase. Accordingly, current density and power required to provide the higher magnetic fields increase, thus limiting the scalability
FIG. 1 illustrates a section of a typical layout for a memory circuit 100. The memory circuit comprises a set of word lines 102 and a set of bit lines 104. The set of bit lines 104 overlies the set of word lines 102 to define crossover zones 108. Addressable magnetic storage elements 110 are disposed within the crossover zones 108. Current drivers 106 are provided for the bit lines 104 and the word lines 102. A low line width for the set of word lines 102 and the set of bit lines 104 results in excessively high line resistance, while an excessive area of the crossover zones 108 can degrade the magnetic flux efficiency, due to low current density. Hence, memory cell designers are faced with the dichotomy of high line resistance and degraded magnetic flux efficiency.